1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and more particularly to a semiconductor integrated circuit device on which an asynchronous interface like SRAM (Static Random Access Memory) using a ferroelectric memory, DRAM (Dynamic Random Access Memory), etc., in a memory core section is mounted.
2. Description of the Related Art
In order to enhance the integration density while application compatibility with an existing SRAM is maintained, a pseudo-SRAM using a ferroelectric memory or DRAM in a memory core section is commercialized. Among the conventional pseudo-SRAMs, a synchronous type SRAM in which the operation of an internal circuit is controlled by use of a clock signal generated in a time series fashion in the internal portion of the device according to an external input signal, for example, an external chip enable signal /CE is dominant.
In recent years, the demand for pseudo-SRAMs used to form portable telephones (cellular system) becomes stronger. In the pseudo-SRAMs used to form portable telephones, the demand for an asynchronous type pseudo-SRAM which can be operated even asynchronously with respect to an external input signal is strong.
In order to realize an asynchronous type pseudo-SRAM, the operation as shown by a timing chart of FIGS. 1A and 1B is required. FIG. 1A shows a read operation and FIG. 1B shows a write operation.
In order to realize the read operation and write operation as shown in FIGS. 1A and 1B, the following configuration can be considered. That is, a plurality of ATD circuits (Address Transition Detecting circuits) which detect the transition of an address are provided and the address transition is detected by use of the ATD circuits. An internal chip enable signal INCE which controls the internal circuit is generated based on a logical product signal ATDSUM obtained as the result of detection. Signals used to drive word lines WL and plate lines PL are generated based on the internal chip enable signal INCE in a time series fashion so as to control the operation of the internal circuit.
In this case, cycle time which is defined by the external input signals (which are the external chip enable signal /CE and address signal) is freely set. However, since the internal chip enable signal INCE formed by use of a timeout circuit (time is constant) is used to control the internal operation, the cycle time becomes constant.
With the above configuration, no problem occurs in the case of the read operation, but a limitation is put on the write operation. The limitation is explained in detail below. As shown in the timing chart of FIG. 1B, the write operation is performed when the external chip enable signal /CE is set at the “L” level and the external write enable signal /WE is set at the “L” level. However, for example, in the case of a pseudo-SRAM having a memory core section configured by use of a ferroelectric memory, data can be written into a cell only in a period during which a plate line PL is being pulse-driven after a word line WL is selected.
As a result, even if the write operation is performed in a period other than the period defined by the above condition, no data can be written into the cell. Therefore, it is necessary to write data after the external write enable signal /WE is set at the “L” level in the write possible period.
Thus, with the conventional configuration in which the signal used to control the operation of the internal circuit is generated by use of the timeout circuit, since the cycle time of the internal circuit is determined constant, the degree of freedom of the write operation is lowered and the operability by the user may be lowered.
Further, as one method of the write operation, a delayed write (or late write) method is known (for example, refer to U.S. Pat. No. 5,748,558). In the delayed write method, only the operation for fetching a given write address and write data into the internal portion of the semiconductor memory device is performed in an operation cycle in which a write request is given from the exterior and the write address and write data are kept held in the internal portion until a write request is next input. Then, the actual write operation into a memory cell is not performed in the present operation cycle, but performed in an operation cycle in which a next write request is input. That is, the method is to delay the write operation with respect to the memory cell to an operation cycle in which a next write request is input.
The delayed write method is considered to attain high speed access to a synchronous type or asynchronous type semiconductor memory device. It is used in a semiconductor memory device having a special high-speed specification such as a synchronous specification. Particularly, in the case of a memory core such as an SRAM which performs non-destructive reading, since it is only required to perform the operation of reading out or rewriting data latched in a cell, the method can be easily applied.
FIG. 2 is a timing chart for illustrating the operation of a semiconductor memory device in which the above delayed write method is used. The write operation is started when the external chip enable signal /CE is set to the “L” level and the external write enable signal /WE is set to the “L” level. In the write operation, an address “A-1” which is used for the write process into a memory cell array and write data “D-1” on an I/O line corresponding to the address “A-1” are supplied to and held in a data register.
Next, when the external write enable signal /WE is set to the “H” level, a word line WL corresponding to an address A0 of the memory cell array is driven and data is read out and supplied onto the bit line. The data read out onto the bit line is amplified by a sense amplifier and then output onto the I/O line as read data Q0.
After this, when the external write enable signal /WE is set to the “L” level, the write operation is performed by use of the address “A-1” and write data “D-1” held in the data register by the write operation which is performed one cycle before the present cycle. That is, a word line WL corresponding to the address “A-1” of the memory cell array is driven and write data “D-1” is read out onto the bit line via the sense amplifier. Thus, the operation of writing data into the memory cell is performed.
After the end of the write operation, an address A1 to be written in the present cycle and write data D1 on an I/O line corresponding to the address A1 are supplied to and held in the data register.
After this, the read operation and write operation which are similar to those described above are alternately performed.
However, with the above method, average read/write access time can be shortened, but the write operation is delayed by at least one cycle. Since the write operation is not performed until a write request is input if the read operations are successively performed, there occurs a possibility that write data cannot be written. This is because it is necessary to execute (n+1) write operation cycles without fail in order to perform n write operations.
Therefore, in a semiconductor memory device of synchronous specification, a period (dead cycle) in which no operation is performed is inserted between the read cycle and the write cycle without fail. As a result, a limitation is imposed on the application method and it is not versatile.
Further, a semiconductor memory device in which the above delayed write method is applied to a pseudo-SRAM using a DRAM core is also known (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. P2001-357671). However, in the case of a memory core such as a DRAM or ferroelectric memory in which destructive reading is performed, it is necessary to provide time (which is generally referred to as precharge time) required for rewriting cell data after the read (write) operation. In addition, it takes a certain time after the access operation is started until a state in which data can actually be written into the cell is set. Further, since the DRAM is a volatile memory, the refresh operation is also required.
Therefore, since vacant time in which no operation is performed is not provided in one cycle, the delayed write method cannot effectively exhibit the effect in a device other than the device corresponding to a special specification such as the synchronous specification. Further, even if the delayed write method is used, the limitation that the write possible time is only a period during which a plate line PL is being pulse-driven after a word line WL is selected is not reduced or removed in the case of a pseudo-SRAM having a memory core section configured by a ferroelectirc memory, for example, in a system using the timeout circuit to control the internal operation as described above. That is, data can be written into the cell only in a period during which the plate line PL is being pulse-driven after the word line WL is selected.
As described above, when the delayed write method is used, the degree of freedom of the write operation in the pseudo-SRAM using a DRAM or ferroelectirc memory is lowered and the operability by the user is lowered.
Further, as described above, with the conventional semiconductor integrated circuit device having the pseudo-SRAM mounted thereon, there occurs a problem that the limitation is imposed on the write operation and the operability thereof by the user is lowered if the asynchronous operation is performed.